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CLASSIFIED:
Logic Verification Engineer |
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| Duration |
: 60 Day(s) |
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: Hyderabad |
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| Description : |
COMPANY NAME: QualCore Logic Ltd.,
EXPERIENCE: 3-8
SALARY: Negotiable
DESCRIPTION:
Responsibilities: - Develop and run Logic Verification Test for FPGA chip - Simulate HDL designs using Modelsim simulator tool - Debug using schematic tracer and waveform viewer tools - Automate the simulation environment using perl - Document the tests Requirements: - Experience in verification at gate level - Strong analytical and problem solving skills - Hardware description languages (Verilog and VHDL) - ASIC/FPGA design flow and methodology (HDL, synthesis, static timing analysis, constraining, place and route) - Unix, Make, Revision Control (CVS), Perl, TCL - Must be able to document work by writing test plan and test reports - Basic knowledge of semiconductor technologies - Knowledge of FPGA architectures is a plus - Knowledge of Programming/software skills in C/C++ is a plus |
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